rev. 4261a?aero?07/03 1 features comprehensive library of standard logic and i/o cells ATC18RHA core and i/o cells designed to operate with v dd = 1.8v sparing 0.15v as main target operating conditions io33 pad libraries provide interfaces to 3v environments memory cells compiled to the precise requirements of the design edac library seu hardened dff?s cold sparring buffers high speed lvds buffers pci buffers predefined die sizes to accommodate specified packages and esa (european space agency) multi-project wafer services mqfp package up to 352 pins (340 signal pins) mcga packages up to 625 pins (581 signal pins) assurance programs will allow ? testing flight models to scc b and qml q & v ? monitoring heavy ions latch-up immunity and total dose capability better than 100 krads. description the atmel ATC18RHA is fabricated on a proprietary 0.18 m, up to six-layer-metal cmos process intended for use with a supply voltage of 1.8v 0.15v. table 1 shows the range for that atmel library cells have been characterized. the atmel cell libraries and megacell compilers have been designed in order to be compatible with each other. simulation representations exist for three types of operat- ing conditions. they correspond to three characterization conditions defined as follows: min conditions: ?t j = -55c ? v dd (cell) = 1.95v ? process = fast typ conditions: ?t j = +25c ?v dd (cell) = 1.8v ? process = typ max conditions: ?t j = +125c ?v dd (cell) = 1.65v ? process = slow table 1. recommended operating conditions symbol parameter conditions min typ max unit v dd dc supply voltage core and standard i/os 1.65 1.8 1.95 v v dd3.3 dc supply voltage 3v interface i/os 3 3.3 3.6 v v i dc input voltage 0 v dd v v o dc output voltage 0 v dd v temp operating free air temperature range military -55 +125 c rad. hard 0.18 m cmos cell-based asic for space use ATC18RHA advance information
2 ATC18RHA 4261a?aero?07/03 delays to tri-state are defined as delay to turn off (vgs < vt) of the driving devices. output pad drain current corresponds to the output current of the pad when the output voltage is v ol or v oh . the output resistor of the pad and the voltage drop due to access resistors (in and out of the die) are taken into account. in order to have accurate timing estimates, all characterization has been run on electrical netlists extracted from the lay- out database. standard cell library sclib the atmel standard cell library, sclib, contains a comprehensive set of a combination of logic and storage cells. the sclib library includes cells that belong to the following categories: buffers and gates multiplexers standard and seu hardened flip-flops standard and seu hardened scan flip-flops latches adders and subtractors decoding the cell name table 2 shows the naming conventions for the cells in the sclib library. each cell name begins with either a two-, three-, or four-letter code that defines the type of cell. this indicates the range of standard cells available. table 2. cell codes code description code description ad adder invb balanced inverter ah half adder invt inverting tri-state buffer as adder/subtractor la d latch an and gate mi inverting multiplexer aoi and-or-invert gate mx multiplexer aon and-or-and-invert gates nd nand gate aor and-or gate nr nor gate bufb balanced buffer oai or-and-invert gate buff non-inverting buffer oan or-and-or-invert gates buft non-inverting tri-state buffer or or gate cg carry generator ora or-and gate clk2 clock buffer sd multiplexed scan d flip-flop df d flip-flop srla set/reset latches with nand input dla dual input latches su subtractor h... seu hardened versions xn exclusive nor gate inv0 inverter xr exclusive or gate
3 ATC18RHA 4261a?aero?07/03 cell matrices table 3 and table 4 provide a quick reference to the storage elements in the sclib library. note that all storage elements feature buffered clock inputs and buffered output. table 3. d flip-flops macro name set clear enabled d input 1xdrive 2xdrive single output seu hardened dfbrbx ?? ?? dfcrbx ??? hdfbrbx ?? ?? ? hdfcrbx ???? dfnrbx ?? hdfvrbx ?? ? dfprbx ??? hdfprbx ???? denrqx ???? table 4. scan flip-flops macro name set clear 1xdrive 2xdrive single output seu hardened sdbrbx ???? sdcrbx ??? hsdbrbx ???? ? hsdcrbx ??? ? sdnrbx ?? hsdnpbx ?? ? sdnrqx ??? hsdnrqx ?? ?
4 ATC18RHA 4261a?aero?07/03 input/output pad cell libraries io18lib and io33lib the atmel input/output cell library, io18lib, contains a comprehensive list of input, out- put, bi-directional and tri-state cells. the ATC18RHA (1.8v) cell library includes one special sets of i/o cells and io33lib, for interfacing with external 3.3v devices. they will encompass the following types of cells: bi-directional tri-state outport outputs inputs pci pecl lvds (eia-644) all buffers will be capable of being used as ?cold sparing? buffers. compiled memories based on virage logic memory compilers, for synchronized memories. its maximum memory size compilation capability is: a set of edac can be used in combination with these memories so as to alleviate their seu susceptibility. synthesized memory the synthesis of memories is based on atmel genesys within the gateaid software. it must be used only for small memories and when seu hardened cells are needed. the maximum memory sizes are as follows: sram 16k x 32 bits dpram 8k x 32 bits tpsf 1k x 16 bits ram 4k bits tpram 4k bits dpram 2k bits
5 ATC18RHA 4261a?aero?07/03 design flow though only modelsim and ncsim will be used as the golden simulators, the design kit will inlcude the data and libraries needed for the following tools: the design flow can be described in two sections: the front-end done at the customer?s premises the back-end at atmel technical centers, provided that the front-end activity has been validated and accepted by atmel during the logic review (lr) meeting. the following table lists the activities and tools that will be used during the front-end design. tool supplier purpose gateaid2 ? atmel atmel support tools modelsim ? mentor vhdl ? /vital ? rtl + gate level simulation ncsim ? cadence verilog ? rtl + gate level simulation design compiler ? synopsys ? hdl synthesis buildgates ? cadence ? hdl synthesis power compiler synopsys synthesis power optimization dft suite mentor ? scan+atpg (fastscan), jtag (bsd- architect), bist (mbist-architect) fe-ultra cadence floor-planning, physical knowledgeable synthesis, layout prototyping primetime ? synopsys static timing analysis formality synopsys equivalence checking, formal proof function tool supplier rtl simulation modelsim mentor nc-sim cadence code coverage vhdl-cover transeda rtl to gate synthesis design-compiler synopsys build-gates cadence power optimization power-compiler synopsys power analysis prime-power synopsys test insertion + atpg dft-suite mentor gate level simulation modelsim mentor nc-sim cadence netlist translation netcvt atmel design rules check star atmel
6 ATC18RHA 4261a?aero?07/03 the following table lists the activities and the tools that will be used during the back-end design: activities function tool supplier bonding diagram array definition mgtechgen atmel pads coordinates paco atmel bonding diagram pimtool atmel pads preplacement p2def atmel periphery check cap atmel ibis model genibis atmel physical implementation blocks preplacement silver atmel virtual layout prototyping first encounter cadence physically knowledgeable synthesis pks cadence power routing snow atmel placement qplace cadence scan chains ordering qp/scan cadence placement-driven violations fix qp/opt cadence clock tree synthesis ctgen cadence routing nanoroute cadence parasitics extraction hyperextract cadence final violations fix qp/opt cadence eco place & route silicon ensemble cadence layout edition silver atmel 3d extraction fire&ice cadence
7 ATC18RHA 4261a?aero?07/03 final verifications static timing analysis primetime synopsys equivalence checking formality synopsys back-annotated simulation modelsim mentor nc-sim cadence consumption analysis mgcomet atmel power scheme check voltagestorm cadence test patterns patform atmel gdsii generation se2gds atmel cross-talk analysis celtic cadence cross-talk errors fix silicon ensemble cadence final analysis signalstorm cadence activities function tool supplier
printed on recycled paper. ? atmel corporation 2003. all rights reserved. atmel, the atmel logo, and combinations thereof are regis- tered trademarks of atmel corporation or its subsidiaries. cadence, verilog, and pearl are registered trademarks of cadence design systems. synopsys and primetime are registered trademarks of synopsys inc.. buildgates is a registered trademark of ambit design systems inc.. ctgen is a registered trademarks of nec corporation. other terms and product names may be the trademarks of others. disclaimer. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standard warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detaile d herein at any time without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implic ation. atmel?s products are not authorized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 4261a?aero?07/03 /0m
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